A semiconductor electronic device including one or more semiconductor integrated circuit chips--such as a silicon semiconductor integrated circuit chip, or a multichip assembly composed of two or more interconnected silicon semiconductor integrated circuit chips mounted on a common interconnection substrate, or at least one such chip mounted on another such chip--is very fragile. It not only requires mechanical support but also requires electrical access to external circuitry via a multiplicity of input-output ("I/O") terminals or metallic pads of the electronic device. Typically this access is supplied, among other things, by means of a circuit board upon which the electronic device is mounted, whereby an assembly is formed. This access itself can also include very fragile wire bonds. The circuit board can take such forms as a printed circuit board or a laminated multilayer (multi-metallization-level) circuit board, the latter also being known as a "lead-frame" board. In addition, if desired, the lead-frame-board is mechanically supported by and electrically connected to, such as by means of a solder bump (globule) array or by a plug-in pin grid array, a so-called "mother board" typically having a much larger area than that of the lead-frame board; and there can be located upon this mother board a number of other electrically interconnected chips or assemblies as well as a number of interconnected lumped electrical elements such as capacitors, transformers, and resistors that cannot be conveniently (if at all) integrated into the chips or multichip assemblies, as well as plugs and connectors.
In order to package the device including the one or more very fragile chips, as well as the very fragile interconnections to the chip(s) such as wire bonds, care must be taken not to injure the chips or the interconnections.
U.S. Pat. No. 5,241,133, issued to William B. Mullen, III, et al. on Aug. 31, 1993, discloses an electronic device assembly in which a silicon integrated circuit chip is electrically connected to metallization located on an underlying printed circuit board by means of gold wire bonds. At the same time, to provide mechanical support of the silicon chip, a chip-bonding-metallization pad is located on the circuit board at a location underlying the chip, and the chip is attached to this metallization pad by means of a conductive adhesive. The lateral extent of this chip-bonding-metallization pad is almost as large as that of the chip. A problem that arises in the resulting assembly of the circuit board and the chip stems from a mismatch in thermal expansion coefficients between the board and the chip, whereby the board is undesirably stressed by the chip. The larger the lateral dimensions of the chip, the more severe the problem becomes: thermal expansion is proportional to length.
The aforementioned patent further teaches that a metallic stiffener, in the form of a plate, having a relatively high flexural modulus (in excess of about 2,000,000 psi) and coated on both sides with the adhesive, can be inserted between the metallization pad and the semiconductor chip in order to reduce the mechanical stress in the circuit board caused by the mismatch between the aforementioned thermal expansion coefficients. However, because of the inflexibility of the stiffener itself, to the extent that stress is thereby reduced in the silicon chip, undesirable strain will still be produced in the underlying circuit board. This strain is further undesirable when the circuit board is supported on a mother board by means of a solder bump array: thermal cycling during electrical operations of the chip will produce expansion-contraction cycling of the circuit board, whereby the solder bumps tend to suffer from metal fatigue and ultimate failure.
The aforementioned patent also teaches that the foregoing assembly (of silicon chip electrically connected to, and physically mounted on, the printed circuit board) is encapsulated on its top surface with a non-pliant-when-cool molding compound by means of a molding machine, in order to seal (encapsulate) the assembly and to seal the silicon chip against the ambient atmosphere as known in the art. However, the thermal expansion coefficient of the molding component cannot be equal to both that of the silicon chip and that of the (thermally mismatched) printed circuit board. Thermal cycling during electrical operations of the chip therefore will tend to cause undesirable stresses or strains either in the chip, or in the circuit board, or in both. More specifically, the thermal cycling of the molding compound will tend to cause it, after having been cured, to break away either from the chip, or from the circuit board, or from both, whereby the wire bond located in the neighborhood of such breaking tends to break. Also, the high pressure and temperature of the molding compound during molding tends to sweep away the wire bonds or to deform them such that they form a short circuit.
U.S. Pat. No. 5,473,512 (Degani 20-11-3-3) teaches an electronic device package that alleviates the problems stemming from the mismatch of the thermal expansion coefficients and that is relevant to this patent.